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Automotive PSoC Programmable System-on-Chip
Features
CY8C20234 (R)
Low power CapSense(R) block Configurable capacitive sensing elements Supports combination of CapSense buttons, sliders, touchpads, and proximity sensors AEC qualified Powerful Harvard architecture processor M8C processor speeds up to 12 MHz Low power at high speed 3.0V to 5.25V operating voltage Automotive temperature range: -40C to +85C Flexible on-chip memory 8 KB of Flash program storage, 1000 erase/write cycles 512 bytes of SRAM data storage Partial Flash updates Flexible protection modes In-System Serial Programming (ISSP) Complete development tools Free development tool (PSoC DesignerTM) Full featured, In-Circuit Emulator (ICE) and Programmer Full speed emulation Complex breakpoint structure 128 KB trace memory Precision, programmable clocking Internal 5% 6/12 MHz oscillator Internal low speed, low power oscillator for Watchdog and Sleep functionality Programmable pin configurations 20 mA Sink on all General Purpose I/O (GPIO) Pull up, High Z, open drain, and strong drive modes on all GPIO Up to 13 analog inputs on GPIO Configurable inputs on all GPIO Selectable, Regulated Digital I/O on Port 1 * 3.0V, 2.4V, and 1.8V Regulation Available * Up to 5 mA Source on Port 1 GPIO Versatile analog mux Common internal analog bus Simultaneous connection of I/O combinations Comparator noise immunity

Additional system resources Configurable communication speeds * I2CTM: Selectable to 50 kHz, 100 kHz, or 400 kHz * SPI: Configurable between 46.9 kHz and 12 MHz 2 I C slave SPI master and SPI slave Watchdog and Sleep timers Internal voltage reference Integrated supervisory circuit
Logic Block Diagram
Port 3 Port 2 Port 1 Port 0 Config LDO
PSoC CORE
System Bus
Global Analog Interconnect SRAM 512 Bytes Interrupt Controller SROM Flash 8K Sleep and Watchdog
CPU Core (M8C)
6/12 MHz Internal Main Oscillator
ANALOG SYSTEM
CapSense Block
Analog Ref.
I2C Slave/SPI Master-Slave
POR and LVD System Resets
Analog Mux
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 001-54650 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 30, 2010
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Contents
Features ............................................................................. 1 Logic Block Diagram ........................................................ 1 PSoC(R) Functional Overview ........................................... 3 PSoC Core .................................................................. 3 CapSense Analog System .......................................... 3 Additional System Resources ..................................... 4 Getting Started .................................................................. 4 Application Notes ........................................................ 4 Development Kits ........................................................ 4 Training ....................................................................... 4 Cypros Consultants ..................................................... 4 Solutions Library .......................................................... 4 Technical Support ....................................................... 4 Development Tools .......................................................... 5 PSoC Designer Software Subsystems ........................ 5 In-Circuit Emulator ....................................................... 5 Designing with PSoC Designer ....................................... 6 Select Components ..................................................... 6 Configure Components ............................................... 6 Organize and Connect ................................................ 6 Generate, Verify, and Debug ....................................... 6 Document Conventions ................................................... 7 Units of Measure ......................................................... 7 Numeric Naming .......................................................... 7 Pinouts .............................................................................. 8 16-Pin Part Pinout ....................................................... 8 Electrical Specifications .................................................. 9 Absolute Maximum Ratings ....................................... 10 Operating Temperature ............................................. 10 DC Electrical Characteristics ..................................... 11 AC Electrical Characteristics ..................................... 14 Packaging Information ................................................... 18 Thermal Impedances ................................................. 18 Solder Reflow Peak Temperature ............................. 18 Development Tool Selection ......................................... 19 Software .................................................................... 19 Development Kits ...................................................... 19 Evaluation Tools ........................................................ 19 Device Programmers ................................................. 20 Accessories (Emulation and Programming) .............. 20 Ordering Information ...................................................... 21 Ordering Code Definitions ............................................. 21 Document History Page ................................................. 22 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support ....................... 23 Products .................................................................... 23 PSoC Solutions ......................................................... 23
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PSoC(R) Functional Overview
The PSoC family consists of many Programmable System-on-Chip with on-chip controller devices. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one low cost single chip programmable component. A PSoC device includes configurable analog and digital blocks and programmable interconnect. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture for this device family, as shown in Figure 1, consists of three main areas: the Core, the System Resources, and the CapSense Analog System. A common versatile bus enables connection between I/O and the analog system. Each CY8C20x34 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 13 GPIO are also included. The GPIO provide access to the MCU and analog mux.
Figure 1. Analog System Block Diagram
ID AC
Analog Global Bus
Vr R eferenc e Buffer
C internal
C om parator
Mux Mux
R efs
PSoC Core
The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, Internal Main Oscillator (IMO), and Internal Low speed Oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard architecture microprocessor. System Resources provide additional capability such as a configurable I2C slave, SPI slave, or SPI master communication interface and various system resets supported by the M8C. The Analog System consists of the CapSense(R) PSoC block and an internal analog reference. Together they support capacitive sensing of up to 13 inputs.
C ap Sens e C ounters
C SC LK IMO C apSens e C lock Selec t R elaxation O s c illator (RO)
Analog Multiplexer System The Analog Mux Bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

CapSense Analog System
The Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins is completed quickly and easily across multiple ports.
Complex capacitive sensing interfaces such as sliders and touch pads Chip-wide mux that enables analog input from any I/O pin Crosspoint connection between any I/O pin combination
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Additional System Resources
System Resources provide additional capability useful for complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource are presented below.
Application Notes
Application notes are an excellent introduction to the wide variety of possible PSoC designs and are available at http://www.cypress.com.
There is a digital module in CY8C20x34 devices that implements an I2C slave, SPI slave, or SPI master interface.The I2C slave mode provides 0 to 400 kHz communication over two wires. The SPI master and slave modes provide communication over three or four wires at frequencies of 46.9 kHz to 12 MHz (lower for a slower system clock). Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels, while the advanced Power On Reset (POR) circuit eliminates the need for a system supervisor. An internal voltage reference provides an absolute reference for capacitive sensing. The 3.0V/2.4V/1.8V fixed output, low dropout regulator (LDO) provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO.
Development Kits
PSoC Development Kits are available online from Cypress at http://www.cypress.com and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and workshops) is available online at http://www.cypress.com. The training covers a wide variety of topics and skill levels to assist you in your designs.

Cypros Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to http://www.cypress.com and refer to CYPros Consultants.
Getting Started
The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the Technical Reference Manual for this PSoC device. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at http://www.cypress.com.
Solutions Library
Visit our growing library of solution focused designs at http://www.cypress.com. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase articles and forums at http://www.cypress.com. If you cannot find an answer to your question, call technical support at 1-800-541-4736.
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Development Tools
PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family.
Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.
PSoC Designer Software Subsystems
System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE). Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug
Organize and Connect
You can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer's output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.
Select Components
Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called "drivers" and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called "user modules". User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
Configure Components
Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design.
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Document Conventions
Table 1 lists the acronyms that are used in this document. Table 1. Acronyms Used Acronym AC API CPU DC GPIO GUI ICE ILO IMO I/O LSb LVD MSb POR PPOR PSoC SLIMO SRAM Description Alternating Current Application Programming Interface Central Processing Unit Direct Current General Purpose I/O Graphical User Interface In-Circuit Emulator Internal Low Speed Oscillator Internal Main Oscillator Input Or Output Least Significant Bit Low Voltage Detect Most Significant Bit Power On Reset Precision Power On Reset Programmable System-on-Chip Slow IMO Static Random Access Memory
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3 on page 9 lists all the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers are also represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, `01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or `0x' are in decimal format.
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Pinouts
This section describes, lists, and illustrates the CY8C20x34 PSoC device pins and pinout configurations. The automotive CY8C20x34 PSoC device is available in the packages listed and shown in the following tables. Every port pin (labeled with a "P") is capable of digital I/O and can connect to the common analog bus. However, Vss, Vdd, and XRES are not capable of digital I/O.
16-Pin Part Pinout
Figure 2. CY8C20234 16-Pin PSoC Device
P0[1], AI P0[3], AI P0[7], AI Vdd AI, P2[5] AI, P2[1] I2C SCL, SPI SS, AI, P1[7] I2C SDA, SPI MISO, AI, P1[5] 1 2 3 4 16 15 14 13
QFN
5 6 7 8
12 11 10 9
P0[4], AI XRES P1[4], AI, EXTCLK P1[2], AI
Table 2. Pin Definitions - CY8C20234 16-Pin (QFN)
Pin No. Type Digital Analog Name Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I/O I/O I/OH I/OH I/OH I/OH Power I/OH I/OH I/OH Input I/O Power I/O I/O I/O
I I I I I I I I I I I I I
P2[5] P2[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] XRES P0[4] Vdd P0[7] P0[3] P0[1]
Integrating Input Supply Voltage Optional External Clock Input (EXTCLK) Active High External Reset with Internal Pull Down I2C Serial Clock (SCL), SPI Slave Select (SS) I2C Serial Data (SDA), SPI Master-In-Slave-Out (MISO) SPI Serial Clock (SCLK) ISSP-SCLK[1], I2C Serial Clock (SCL), SPI Master-Out-Slave-In (MOSI) Ground Connection ISSP-SDATA[1], I2C Serial Data (SDA)
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Note 1. These are the ISSP pins, that are not High Z after exiting a reset state. See the PSoC Technical Reference Manual for CY8C20x34 devices for details.
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SPI SCLK, AI, P1[3] I2C SCL, SPI MOSI, AI, P1[1] Vss I2C SDA, AI, P1[0]
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Electrical Specifications
This section presents the DC and AC electrical specifications of the automotive CY8C20x34 PSoC device. For the latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com. Specifications are valid for -40C TA 85C and TJ 100C as specified, except where mentioned. Refer to Table 12 on page 14 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 3. Voltage versus CPU Frequency Figure 4. IMO Frequency Trim Options
5.25
5.25
SLIMO Mode=1
4.75 Vdd Voltage (V)
SLIMO Mode=0
lid ing Va at er ion Op eg R
4.75 Vdd Voltage (V)
3.6
SLIMO Mode=1
3.0
SLIMO Mode=0
3.0
0 750 kHz 3 MHz CPU Frequency (nominal setting) 6 MHz 12 MHz
0 6 MHz IMO Frequency 12 MHz
Table 3 lists the units of measure that are used in this section. Table 3. Units of Measure Symbol C dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol W mA ms mV nA ns nV pA pF pp ppm ps sps V Unit of Measure microwatts milliampere millisecond millivolts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts
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Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 4. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Min -55 Typ 25 Max +100 Units Notes C Higher storage temperatures reduces data retention time. Recommended storage temperature is +25C 25C. Extended duration storage temperatures above 65C degrades reliability. C
TBAKETEMP Bake Temperature
-
125
TBAKETIME
Bake Time
TA Vdd VIO VIOZ IMIO ESD LU
Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch Up Current
See package label -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 -
-
See package label 72
Hours C V V V mA V mA
- - - - - - -
+85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 - 200
Human Body Model ESD.
Operating Temperature
Table 5. Operating Temperature Symbol TA TJ Description Ambient Temperature Junction Temperature Min -40 -40 Typ - - Max +85 +100 Units Notes C C The temperature rise from ambient to junction is package specific. See Table 20 on page 18. The user must limit the power consumption to comply with this requirement.
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DC Electrical Characteristics
DC Chip Level Specifications Table 6 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 6. DC Chip Level Specifications Symbol Vdd IDD12 IDD6 ISB Description Supply Voltage Supply Current, IMO = 12 MHz Supply Current, IMO = 6 MHz Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and ILO Active. Min 3.0 - - - Typ - 1.5 1 2.8 Max 5.25 2.5 1.5 5 Units V mA mA A Notes See Table 9 on page 12. Conditions are Vdd = 3.0V, TA = 25C, CPU = 12 MHz. Conditions are Vdd = 3.0V, TA = 25C, CPU = 6 MHz Vdd = 3.3V, -40C TA 85C
DC General Purpose I/O Specifications Table 7 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 7. DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 VOH4 VOH5 Description Pull Up Resistor High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with 3.0V LDO Regulator Enabled High Output Voltage Port 1 Pins with 3.0V LDO Regulator Enabled High Output Voltage Port 1 Pins with 2.4V LDO Regulator Enabled High Output Voltage Port 1 Pins with 2.4V LDO Regulator Enabled High Output Voltage Port 1 Pins with 1.8V LDO Regulator Enabled Min 4 Vdd - 0.2 Vdd - 0.9 Vdd - 0.2 Vdd - 0.9 2.7 Typ 5.6 - - - - 3.0 Max 8 - - - - 3.3 Units Notes k V IOH 10 A, Vdd 3.0V, maximum of 20 mA source current in all I/Os. V IOH 1 mA, Vdd 3.0V, maximum of 20 mA source current in all I/Os. V IOH 10 A, Vdd 3.0V, maximum of 10 mA source current in all I/Os. V IOH 5 mA, Vdd 3.0V, maximum of 20 mA source current in all I/Os. V IOH 10 A, Vdd 3.1V, maximum of 4 I/Os all sourcing 5 mA. V IOH 5 mA, Vdd 3.1V, maximum of 20 mA source current in all I/Os. IOH 10 A, Vdd 3.0V, maximum of 20 mA source current in all I/Os. IOH 200 A, Vdd 3.0V, maximum of 20 mA source current in all I/Os. IOH 10 A 3.0V Vdd 3.6V 0C TA 85C Maximum of 20 mA source current in all I/Os.
VOH6
2.2
-
-
VOH7
2.1
2.4
2.7
V
VOH8
2.0
-
-
V
VOH9
1.6
1.8
2.0
V
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Table 7. DC GPIO Specifications (continued) Symbol VOH10 Description High Output Voltage Port 1 Pins with 1.8V LDO Regulator Enabled Min 1.5 Typ - Max - Units Notes V IOH 100 A. 3.0V Vdd 3.6V. 0C TA 85C. Maximum of 20 mA source current in all I/Os. V IOL 20 mA, Vdd 3.0V, maximum of 60 mA sink current on even port pins (for example, P0[4] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). V V mV nA Gross tested to 1 A pF Package and pin dependent Temperature = 25C pF Package and pin dependent Temperature = 25C
VOL
Low Output Voltage
-
-
0.75
VIL VIH VH IIL CIN COUT
Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
- 2.0 - - 0.5 0.5
- - 140 1 1.7 1.7
0.8 - - 5 5
DC Analog Mux Bus Specifications Table 8 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 8. DC Analog Mux Bus Specifications Symbol RSW Description Switch Resistance to Common Analog Bus Min - Typ - Max 450 Units Notes
DC POR and LVD Specifications Table 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 9. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min - - - 2.34 2.54 2.75 2.85 2.96 - - 4.44 Typ 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 - - 4.73 Max 2.40 2.65 2.95 2.51[3] 2.78[4] 2.99[5] 3.09 3.20 - - 4.93 Units V V V V V V V V V V V Notes Vdd is greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog.
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DC Analog Reference Specifications Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 10. DC Analog Reference Specifications Symbol BG Description Bandgap Reference Voltage Min 1.274 Typ 1.30 Max 1.326 Units V Notes
DC Programming Specifications Table 11 lists the guaranteed minimum and maximum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Flash Endurance and Retention specifications with the use of the EEPROM User Module are valid only within the range: 25C 20C during the Flash Write operation. Refer to the EEPROM User Module data sheet instructions for EEPROM Flash Write requirements outside of the 25C 20C temperature window. Table 11. DC Programming Specifications Symbol Description VddIWRITE Supply Voltage for Flash Write Operations IDDP Supply Current During Programming or Verify VILP Input Low Voltage During Programming or Verify VIHP IILP IIHP VOLV VOHV Input High Voltage During Programming or Verify Input Current when Applying VILP to P1[0] or P1[1] During Programming or Verify Input Current when Applying VIHP to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Min 3.0 - - 2.2 - - - Vdd -1.0 1,000 128,000 10 Typ - 5 - - - - - - - - - Max - 25 0.8 - 0.2 1.5 0.75 Vdd - - - Units V mA V V mA mA V V - Erase/write cycles per block. - Erase/write cycles. Years Driving internal pull down resistor. Driving internal pull down resistor. Notes
Output High Voltage During Programming or Verify FlashENPB Flash Endurance (per block)[6] FlashENT Flash Endurance (total)[7] FlashDR Flash Data Retention
Notes 3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. 4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. 5. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. 6. The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V to 5.25V. 7. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device.
Document Number: 001-54650 Rev. *D
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AC Electrical Characteristics
AC Chip Level Specifications Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 12. AC Chip-Level Specifications Symbol FCPU1 F32K1 F32KU FIMO12 Description CPU Frequency Internal Low Speed Oscillator (ILO) Frequency ILO Untrimmed Frequency Min 0.71 15 5 Typ - 32 - Max 12.6 64 - Units MHz kHz kHz Notes 12 MHz only for SLIMO Mode = 0 This specification applies when the ILO has been trimmed. After a reset and before the M8C processor starts to execute, the ILO is not trimmed. Trimmed using factory trim values. See Figure 4 on page 9, SLIMO Mode = 0. Trimmed using factory trim values. See Figure 4 on page 9, SLIMO Mode = 1.
Internal Main Oscillator (IMO) Stability for 12 MHz IMO Stability for 6 MHz
11.4
12
12.6
MHz
FIMO6
5.5
6.0
6.5
MHz
DCIMO DCILO TXRST TPOWERUP
Duty Cycle of IMO ILO Duty Cycle External Reset Pulse Width Time between end of POR state and CPU code execution
40 20 10 - -
50 50 - - 16
60 80 - 250 100
% % s V/ms ms Vdd slew rate during power up. Power up from 0V.
SRPOWERUP Power Supply Slew Rate
AC General Purpose I/O Specifications Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 13. AC GPIO Specifications Symbol FGPIO TRise023 TRise1 TFall Description GPIO Operating Frequency Rise Time, Strong Mode, Cload = 50 pF Ports 0, 2, 3 Rise Time, Strong Mode, Cload = 50 pF Port 1 Fall Time, Strong Mode, Cload = 50 pF All Ports Min 0 15 10 10 Typ - - - - Max 6.30 80 50 50 Units MHz ns ns ns Notes Normal Strong Mode, Port 1. Vdd = 3.0V to 3.6V and 4.75V to 5.25V, 10% - 90% Vdd = 3.0V to 3.6V, 10% - 90% Vdd = 3.0V to 3.6V and 4.75V to 5.25V, 10% - 90%
Figure 5. GPIO Timing Diagram
90% GPIO Pin Output Voltage 10%
TRise023 TRise1
TFall
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AC Comparator Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 14. AC Comparator Specifications Symbol TCOMP Description Comparator Response Time, 50 mV Overdrive Min - - Typ - - Max 100 200 Units ns ns Notes Vdd > 3.6V 3.0V Vdd 3.6V
AC External Clock Specifications Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 15. AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.750 38 38 150 Typ - - - - Max 12.6 5300 - - Units MHz ns ns s Notes
AC Programming Specifications Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 16. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TPRGH TPRGC Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Total Flash Block Program Time (TERASEB + TWRITE), Hot Total Flash Block Program Time (TERASEB + TWRITE), Cold Min 1 1 40 40 0 - - - - - - Typ - - - - - 10 40 - - - - Max 20 20 - - 8 40 160 45 50 100 200 Units ns ns ns ns MHz ms ms ns ns ms ms Vdd > 3.6V 3.0V Vdd 3.6V TJ 0C TJ < 0C Notes
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AC SPI Specifications Table 17 and Table 18 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 17. SPI Master AC Specifications Symbol FSCLK DCSCLK TSETUP THOLD TOUT_VAL TOUT_HIGH Parameter SCLK clock frequency SCLK duty cycle MISO to SCLK setup time SCLK to MISO hold time SCLK to MOSI valid time MOSI high time Min - - 40 40 - 40 Typ - 50 - - - - Max 12.6 - - - 40 - Units MHz % ns ns ns ns Notes
Table 18. SPI Slave AC Specifications Symbol FSCLK TLOW THIGH TSETUP THOLD TSS_MISO TSCLK_MISO TSS_HIGH TSS_SCLK TSCLK_SS Parameter SCLK clock frequency SCLK low time SCLK high time MOSI to SCLK setup time SCLK to MOSI hold time SS low to MISO valid SCLK to MISO valid SS high time Time from SS low to first SCLK Time from last SCLK to SS high Min - 39.6 39.6 30 50 - - 50 2/FSCLK 2/FSCLK Typ - - - - - - - - - - Max 12.6 - - - - 153 125 - - - Units MHz ns ns ns ns ns ns ns ns ns Notes
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AC I2C Specifications Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C. These are for design guidance only. Table 19. AC Characteristics of the I2C SDA and SCL Pins Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Max 100[8] - - - - - - - - - Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100[9] 0.6 1.3 0 Max 400[8] - - - - - - - - 50 Units kHz s s s s s ns s s ns
Figure 6. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA T LOWI2C T SUDATI2C T HDSTAI2C
T SPI2C T BUFI2C
SCL T HDSTAI2C T HDDATI2C T HIGHI2C T SUSTAI2C T SUSTOI2C
S
Sr
P
S
Notes 8. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 12 MHz, nominal. If SysClk is at a lower frequency, then the FSCLI2C specification adjusts accordingly. 9. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-54650 Rev. *D
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Packaging Information
This section illustrates the packaging specifications for the automotive CY8C20x34 PSoC device along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Figure 7. 16-Pin Chip On Lead 3 x 3 mm Package Outline (Sawn)
001-09116 *E
Important Note For information on the preferred dimensions for mounting QFN packages, see the application note "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.
Thermal Impedances
Table 20 illustrates the minimum solder reflow peak temperature to achieve good solderability. Table 20. Thermal Impedances Per Package
Package 16 QFN Typical JA 46 C/W
[9]
Solder Reflow Peak Temperature
Table 21 illustrates the minimum solder reflow peak temperature to achieve good solderability. Table 21. Solder Reflow Peak Temperature
Package 16 QFN Min Peak Temperature [10] Max Peak Temperature
240 C
260 C
Notes 9. TJ = TA + Power x JA. 10. Higher temperatures is required based on the solder melting point. Typical temperatures for solder are 220 5C with Sn-Pb or 245 5C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Document Number: 001-54650 Rev. *D
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Development Tool Selection
This section presents the development tools available for the CY8C20x34 family.
Software
PSoC Designer At the core of the PSoC development software suite is PSoC Designer. Used by thousands of PSoC developers, this robust software has been facilitating PSoC designs for years. PSoC Designer is available free of charge at http://www.cypress.com. PSoC Designer comes with a free C compiler. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com.
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, an RS-232 port, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
Development Kits
All development kits can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer also supports the advance emulation features. The kit includes: ICE-Cube Unit 28-Pin PDIP Emulation Pod for CY8C29466-24PXI 28-Pin CY8C29466-24PXI PDIP PSoC Device Samples (two) PSoC Designer Software CD ISSP Cable MiniEval Socket Programming and Evaluation board Backward Compatibility Cable (for connecting to legacy Pods) Universal 110/220 Power Supply (12V) European Plug Adapter USB 2.0 Cable Getting Started Guide Development Kit Registration form CY3280-BK1 The Universal CapSense Control Kit is designed for easy prototyping and debug of CapSense designs with pre defined control circuitry and plug-in hardware. The kit comes with a control boards for CY8C20x34 and CY8C21x34 devices as well as a breadboard module and a button(5)/slider module.
CY3210-20X34 Evaluation Pod (EvalPod) PSoC EvalPods are pods that connect to the ICE In-Circuit Emulator (CY3215-DK kit) to allow debugging capability. They can also function as a standalone device without debugging capability. The EvalPod has a 28-pin DIP footprint on the bottom for easy connection to development kits or other hardware. The top of the EvalPod has prototyping headers for easy connection to the device's pins. CY3210-20X34 provides evaluation of the CY8C20x34 PSoC device family.
Document Number: 001-54650 Rev. *D
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Device Programmers
All device programmers are purchased from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. This software is free and can be downloaded from http://www.cypress.com. The kit includes:

CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable
MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
Accessories (Emulation and Programming)
Table 22. Emulation and Programming Accessories Part Number CY8C20234-12LKXA Pin Package 16 QFN Pod Kit [12] Foot Kit [13] Prototyping Module CY3210-20X34 Adapter [14] -
Notes 12. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples. 13. Foot kit includes surface mount feet that is soldered to the target PCB. 14. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is found at http://www.emulation.com.
Document Number: 001-54650 Rev. *D
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Ordering Information
Table 23 lists the automotive CY8C20x34 PSoC device key package features and ordering codes. Table 23. PSoC Device Key Features and Ordering Information Ordering Code CY8C20234-12LKXA Package 16-Pin (3 x 3 x 0.60 mm) Sawn QFN Flash SRAM Digital CapSense Digital Analog Analog XRES (Bytes) (Bytes) Blocks Blocks I/O Pins Inputs Outputs Pin 8K 8K 512 512 0 0 1 1 13 13 13[15] 13[15] 0 0 Yes Yes
CY8C20234-12LKXAT 16-Pin (3 x 3 x 0.60 mm) Sawn QFN (Tape and Reel)
Ordering Code Definitions
CY 8 C 20 xxx- 12 xx
Package Type: Thermal Rating: PX = PDIP Pb-free A = Automotive -40C to +85C SX = SOIC Pb-free C = Commercial PVX = SSOP Pb-free E = Automotive Extended -40C to +125C LFX/LKX = QFN Pb-free I = Industrial AX = TQFP Pb-free CPU Speed: 12 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress
Note 15. Digital I/O pins also connect to the common analog mux.
Document Number: 001-54650 Rev. *D
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Document History Page
Document Title: CY8C20234 Automotive PSoC(R) Programmable System-on-Chip Document Number: 001-54650 Revision ** *A ECN 2743436 2799448 Orig. of Change MASJ/AESA BTK Submission Date 07/24/09 11/05/09 New data sheet. Updated Features section. Updated text of PSoC Functional Overview section. Updated Getting Started section. Made corrections and minor text edits to Pinouts section. Changed the name of some sections to improve consistency. Added clarifying comments to some electrical specifications. Fixed all AC specifications to conform to a 5% IMO accuracy. Made other miscellaneous minor text edits. Deleted some non-applicable or redundant information. Improved and edited content in Development Tool Selection section. Improved the bookmark structure. Changed FlashENT, FOSCEXT, TERASEB, and TWRITE electrical specifications according to MASJ input. Added and slightly modified the expanded SPI AC specifications from 001-05356 Rev *I. Added a table of contents.This revision fixes CDT 61474. Added TPRGH, TPRGC, F32KU, DCILO, and TPOWERUP electrical specifications. Updated the footnotes for Table 11, "DC Programming Specifications," on page 13. Added maximum values and updated typical values for TERASEB and TWRITE electrical specifications. Replaced TRAMP electrical specification with SRPOWERUP electrical specification. Changed FIMO6 electrical specification to have an 8.33% accuracy instead of 5%. Added "Contents" on page 2. This revision fixes CDT 63984. Updated Cypress website links. Updated CapSense Analog System. Removed PSoC Designer 4.4 reference in PSoC Designer Software Subsystems. Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings. Removed DC Low Power Comparator Specifications, AC Analog Mux Bus Specifications, and AC Low Power Comparator Specifications. Updated Packaging Information. Added Solder Reflow Peak Temperature. Removed Third Party Tools and Build a PSoC Emulator into Your Board. Updated links in Sales, Solutions, and Legal Information. Under section "AC Comparator Amplifier Specifications", the caption for spec table changed from "AC Operational Amplifier Specifications" to "AC Comparator Specifications". Also the section heading changed to AC Comparator specifications. Description of Change
*B
2822792
BTK/AESA
12/07/2009
*C
2888007
NJF
03/30/2010
*D
3043236
ARVM
09/30/10
Document Number: 001-54650 Rev. *D
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54650 Rev. *D
Revised March 30, 2010
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PSoC DesignerTM and Programmable System-on-ChipTM are trademarks and PSoC(R) and CapSense(R) are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.
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